As the world pushes further to smaller cheaper and faster devices, the microelectronics industry pushed the limits of the technology. A large number of technologies aroused as an answer to the growing challenge, and the back-end of the line is no exception.
The gradual adaptation of new technologies in the back-end, was replaced by a variety of new packaging methods. These methods tackle the obstacles in a range of approaches.
One of the promising approaches is the “Fan Out” approach. This approach, besides solving the need for increased I/O for the manufactured dice, enables the reduction of manufacturing costs as it requires less of the expensive silicon area.
The fan-out technology has unique requirements that should be met in a low price.
The Wafer Level Fan Out (WLFO) Technology
Referring to FIG. 1—the fundamental WLFO technology is a 2D configuration, based on embedding dies (12 and 13) into a molded wafer (molded material 11), also called “wafer reconstitution.” The molded wafer is processed through a standard WLP flow to create the final IC assembly structure (see FIG. 1). The active surface of the die is coplanar with the mold compound, allowing for the “fan-out” of
redistribution layer (RDL) conductors (14, 15, 16 and 17) such as conductive copper traces and solder ball pads into the molded area using conventional RDL processing. Bumps 18, 19, 20 and 21 are then manufactured the solder ball pads.